Hanrui Li

Hanrui Li

Microelectronics&Artificial Intelligence

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A list of all the posts and pages found on the site. For you robots out there is an XML version available for digesting as well.

Pages

Posts

Future Blog Post

less than 1 minute read

Published:

This post will show up by default. To disable scheduling of future posts, edit config.yml and set future: false.

Blog Post number 4

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

Blog Post number 3

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

Blog Post number 2

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

Blog Post number 1

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

portfolio

publications

Material transporter for microelectronic products within the workshop

Published in Chinese patent, 2020

This work is about an utility patent for material transporter. We designed and developed a material transporter for microelectronic components with a suspended payload rack to drastically reduce vibrations and shaking while transporting the components; specifically, the rack was in a floating state relative to the frame using a buffer system. Drew diagrams of the transporter’s structure in CAD and chose the suitable materials to build the model. Described the design in a detailed document and applied for a new utility patent.

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Real-time Biosignal Recording and Machine-Learning Analysis System

Published in IEEE AICAS, 2022

Biosignal recording and processing systems (BRPSs) are in high demand for numerous applications such as brainmachine interfaces, healthcare, and other clinical applications. However, conventional BRPS can only perform simple operations, such as filtering and denoising, but cannot perform robust machine learning-based analyses in real time. This paper proposes an intelligent BRPS that consists of a signal recording frontend for biosignal acquisition, control and visualization hub, and FPGA board for machine learning acceleration. High-speed Ethernet and PCIe interfaces were used to increase the data transmission rate of the system. Moreover, the integrated accelerator in the FPGA is designed in a single-instruction-multiple-data (SIMD) mode to perform complex machine learning operations in parallel to speed up data-processing tasks. The proposed system is validated for various applications, including EEG-based seizure prediction with a convolutional neural network (CNN), EMGbased gesture recognition with a spiking neural network (SNN), and ECG-based arrhythmia detection with a binary neural network (BNN). Experimental results reveal that this system takes 13 ms to process one-second electrophysiological signals at 512 Hz and 32 channels, thus achieving real-time performance. The proposed BRPS is an open-source and expandable system, and different machine-learning approaches can be configured for diverse applications. Our poster

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Vertically Stacked Nanosheet FET Charge-Trapping Memory and Synapse With Linear Weight Adjustability for Neuromorphic Computing Applications

Published in IEEE Transactions on Electron Devices, 2023

This work shows the feasibility of a vertically stacked nanosheet field effect transistor (NSFET) for charge-trapping memory and artificial synaptic devices. The artificial synapse’s behaviors, long-term potentiation (LTP), and long-term depression (LTD) are analogous to erase (ERS) and program (PGM) of charge-trapping memory, respectively. This NSFET device with a gate length of 50 nm achieves a wider memory window (MW), long retention time for programming, and infinite retention ( > 10 8 s) for ERS operation. The results also show linear synaptic features with nonlinearity values of 2.50 and − 0.42 for LTP and LTD, respectively. Furthermore, the device conductance values are utilized as synaptic weights for image recognition of Modified National Institute of Standards and Technology (MNIST) dataset in neural networks and achieve 93.30% accuracy. These results make it a promising candidate for next-generation charge-trapping memory and neuromorphic computing due to its wide memory window, long retention, high accuracy, and high density.

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talks

teaching

Teaching experience 1

Undergraduate course, University 1, Department, 2014

This is a description of a teaching experience. You can use markdown like any other post.

Teaching experience 2

Workshop, University 1, Department, 2015

This is a description of a teaching experience. You can use markdown like any other post.